On Wed, Apr 13, 2011 at 18:49, Rafael J. Wysocki wrote: > On Thursday, April 14, 2011, Mike Frysinger wrote: >> i guess the trouble for us is that you have one CPU posting writes to >> task->flags (and doing so by grabbing the task's spinlock), but the >> other CPU is simply reading those flags. Âthere are no SMP barriers in >> between the read and write steps, nor is the reading CPU grabbing any >> locks which would be an implicit SMP barrier. Âsince the Blackfin SMP >> port lacks hardware cache coherency, there is no way for us to know >> "we've got to sync the caches before we can do this read". Âby using >> the patch i posted above, we have that signal and so things work >> correctly., > > In theory I wouldn't expect the patch to work correctly, because it replaces > _stronger_ memory barriers with _weaker_ SMP barriers. ÂHowever, looking at > the blackfin's definitions of SMP barriers I see that it uses extra stuff that > should _also_ be used in the definitions of the mandatory barriers. > > In my opinion is an architecture problem, not the freezer code problem. OK, we have a patch pending locally which populates all barriers with this logic, but based on my understanding of things, that didnt seem correct. i guess i'm reading too much into the names ... i'd expect the opposite behavior where "rmb" is only for UP needs while "smp_rmb" is a rmb which additionally covers SMP. -mike _______________________________________________ linux-pm mailing list linux-pm@xxxxxxxxxxxxxxxxxxxxxxxxxx https://lists.linux-foundation.org/mailman/listinfo/linux-pm
