On Wed, Jan 31, 2007 at 12:13:04PM +0100, Andi Kleen wrote: > Matthew Garrett <mjg59 at srcf.ucam.org> writes: > > > > PCI seems to require a delay of 10ms when sequencing from D3 to D0, > > which probably isn't acceptable latency for an "up" state. > > It might be if the interface has been idle for some time > (and the delay is not busy looping of course) Hm. How would this interact with receiving packets? -- Matthew Garrett | mjg59 at srcf.ucam.org
