On Wed, Jan 31, 2007 at 11:13:07AM +0200, Amit Kucheria wrote: > What is the latency in changing between different PCI power states for > peripherals? I'm not sure in the general case, but the power-down path for the ipw2100 involves a static wait of 100ms in ipw2100_hw_stop_adapter(). > Would it be possible e.g. to put the peripheral into a low power state > after each Tx/Rx (with reasonable hyteresis)? Most wireless drivers support some degree of power management at this scale, but (in ipw2100 at least) it's implemented in the firmware so I have absolutely no idea what it's actually doing. > <snip> > > > The situation is slightly more complicated for wired interfaces. As > > previously discussed, we potentially want three interface states (on, > > low power, off) with the intermediate one powering down as much of the > > hardware as possible while still implementing link detection. > > And this low power state is what the HW should be in all the time, > except when it has work to do. PCI seems to require a delay of 10ms when sequencing from D3 to D0, which probably isn't acceptable latency for an "up" state. While there's definitely a benefit to the sort of PM you're describing (it's a model we've already started using on the desktop as far as the CPU goes), I think we still want to be able to expose as much power saving as possible. -- Matthew Garrett | mjg59 at srcf.ucam.org
