- Read the value of PCI_L1SS_CTL1 directly and cache in local variables.
- Replace references to aspm_register_info.l1ss_ctl1 with the variables.
- In pcie_get_aspm_reg() remove reference to aspm_register_info.l1ss_ctl*
- In pcie_get_aspm_reg() remove reading PCI_L1SS_CTL1 and PCI_L1SS_CTL2
- Remove aspm_register_info.(l1ss_ctl1 && l1ss_ctl2)
Note that aspm_register_info.l1ss_ctl2 is eliminated totally since it is
not used.
Signed-off-by: Saheed O. Bolarinwa <refactormyself@xxxxxxxxx>
---
drivers/pci/pcie/aspm.c | 23 ++++++++++-------------
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index d3ad31a230b5..f89d3b2be1c7 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -384,10 +384,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
struct aspm_register_info {
u32 enabled:2;
-
- /* L1 substates */
- u32 l1ss_ctl1;
- u32 l1ss_ctl2;
};
static void pcie_get_aspm_reg(struct pci_dev *pdev,
@@ -397,11 +393,6 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev,
pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &ctl);
info->enabled = ctl & PCI_EXP_LNKCTL_ASPMC;
-
- pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1,
- &info->l1ss_ctl1);
- pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2,
- &info->l1ss_ctl2);
}
static void pcie_aspm_check_latency(struct pci_dev *endpoint)
@@ -527,6 +518,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
struct pci_dev *child = link->downstream, *parent = link->pdev;
struct pci_bus *linkbus = parent->subordinate;
struct aspm_register_info upreg, dwreg;
+ u32 up_l1ss_ctl1, dw_l1ss_ctl1;
if (blacklist) {
/* Set enabled/disable so that we will disable ASPM later */
@@ -549,6 +541,11 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
/* Configure common clock before checking latencies */
pcie_aspm_configure_common_clock(link);
+ pci_read_config_dword(parent, parent->l1ss_cap_ptr + PCI_L1SS_CTL1,
+ &up_l1ss_ctl1);
+ pci_read_config_dword(child, child->l1ss_cap_ptr + PCI_L1SS_CTL1,
+ &dw_l1ss_ctl1);
+
/*
* Re-read upstream/downstream components' register state
* after clock configuration
@@ -592,13 +589,13 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
if (parent->l1ss_cap & child->l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
- if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
+ if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
link->aspm_enabled |= ASPM_STATE_L1_1;
- if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
+ if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
link->aspm_enabled |= ASPM_STATE_L1_2;
- if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
+ if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
- if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
+ if (up_l1ss_ctl1 & dw_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
if (link->aspm_support & ASPM_STATE_L1SS)
--
2.18.4
