Re: Problem with PCIe enumeration of Google/Coral TPU Edge module on Linux

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Hi Bjiorn

I don't see any log of __pci_bridge_assign_resources. This platform
makes use of pci-bridge-emul.c functions. Don't know if that can be
responsible for not calling __pci_bridge_assign_resources(...).

Luís

On Wed, Apr 1, 2020 at 10:20 PM Luís Mendes <luis.p.mendes@xxxxxxxxx> wrote:
>
> Hi Bjorn,
>
> Here is the dmesg output with the new kernel patch:
> https://paste.ubuntu.com/p/7cv7ZcyrnG/
>
> Luís
>
> On Wed, Apr 1, 2020 at 7:16 PM Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote:
> >
> > On Tue, Mar 31, 2020 at 10:28:51PM +0100, Luís Mendes wrote:
> > > I've removed all other PCIe devices to make the analysis easier.
> > > The dmesg with the traces can be found at:
> > > https://paste.ubuntu.com/p/W3m2VQCYqg/
> > >
> > > Didn't find anything new related to BAR0 or BAR2, in the dmesg,
> > > though. Anyway I'm no expert in this, maybe it can give you some
> > > useful information, still.
> >
> > It looks like we assigned the right amount of space to the bridge, but
> > for some reason didn't assign it to the device *below* the bridge.
> >
> > I added a few more messages in this patch.  Can you remove the first
> > one and replace it with this?  This is still based on v5.6-rc1.
> >
> >
> > diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
> > index 8e40b3e6da77..2cdb705752de 100644
> > --- a/drivers/pci/bus.c
> > +++ b/drivers/pci/bus.c
> ...




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