Hi Jean,
On 12/9/19 7:05 PM, Jean-Philippe Brucker wrote:
> For platform devices that support SubstreamID (SSID), firmware provides
> the number of supported SSID bits. Restrict it to what the SMMU supports
> and cache it into master->ssid_bits, which will also be used for PCI
> PASID.
>
> Signed-off-by: Jean-Philippe Brucker <jean-philippe@xxxxxxxxxx>
> ---
> drivers/iommu/arm-smmu-v3.c | 13 +++++++++++++
> drivers/iommu/of_iommu.c | 6 +++++-
> include/linux/iommu.h | 2 ++
> 3 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> index d4e8b7f8d9f4..837b4283b4dc 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -292,6 +292,12 @@
>
> #define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4)
>
> +/*
> + * When the SMMU only supports linear context descriptor tables, pick a
> + * reasonable size limit (64kB).
> + */
> +#define CTXDESC_LINEAR_CDMAX ilog2(SZ_64K / (CTXDESC_CD_DWORDS << 3))
> +
> /* Convert between AArch64 (CPU) TCR format and SMMU CD format */
> #define ARM_SMMU_TCR2CD(tcr, fld) FIELD_PREP(CTXDESC_CD_0_TCR_##fld, \
> FIELD_GET(ARM64_TCR_##fld, tcr))
> @@ -638,6 +644,7 @@ struct arm_smmu_master {
> u32 *sids;
> unsigned int num_sids;
> bool ats_enabled;
> + unsigned int ssid_bits;
> };
>
> /* SMMU private data for an IOMMU domain */
> @@ -2571,6 +2578,12 @@ static int arm_smmu_add_device(struct device *dev)
> }
> }
>
> + master->ssid_bits = min(smmu->ssid_bits, fwspec->num_pasid_bits);
> +
> + if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB))
> + master->ssid_bits = min_t(u8, master->ssid_bits,
> + CTXDESC_LINEAR_CDMAX);
> +
> group = iommu_group_get_for_dev(dev);
> if (!IS_ERR(group)) {
> iommu_group_put(group);
> diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c
> index 026ad2b29dcd..b3ccb2f7f1c7 100644
> --- a/drivers/iommu/of_iommu.c
> +++ b/drivers/iommu/of_iommu.c
> @@ -196,8 +196,12 @@ const struct iommu_ops *of_iommu_configure(struct device *dev,
> if (err)
> break;
> }
> - }
>
> + fwspec = dev_iommu_fwspec_get(dev);
> + if (!err && fwspec)
> + of_property_read_u32(master_np, "pasid-num-bits",
> + &fwspec->num_pasid_bits);
> + }
This patch dedicates to platform devices however I fail to understand,
at that stage, how/when do you retrieve/store the same max capability
for PCI devices?
>
> /*
> * Two success conditions can be represented by non-negative err here:
> diff --git a/include/linux/iommu.h b/include/linux/iommu.h
> index 3a113c5d7394..bd46775c3329 100644
> --- a/include/linux/iommu.h
> +++ b/include/linux/iommu.h
> @@ -581,6 +581,7 @@ struct iommu_group *fsl_mc_device_group(struct device *dev);
> * @ops: ops for this device's IOMMU
> * @iommu_fwnode: firmware handle for this device's IOMMU
> * @iommu_priv: IOMMU driver private data for this device
> + * @num_pasid_bits: number of PASID bits supported by this device
> * @num_ids: number of associated device IDs
> * @ids: IDs which this device may present to the IOMMU
> */
> @@ -589,6 +590,7 @@ struct iommu_fwspec {
> struct fwnode_handle *iommu_fwnode;
> void *iommu_priv;
> u32 flags;
> + u32 num_pasid_bits;
> unsigned int num_ids;
> u32 ids[1];
> };
>
Besides,
Reviewed-by: Eric Auger <eric.auger@xxxxxxxxxx>
Thanks
Eric
