On Sun, Dec 08, 2019 at 10:03:20PM +0100, Remi Pommarel wrote:
> In order to get PCIe working reliably on some AXG platforms, PCIe pll
> cml needs to be enabled. This is done by using the PCIE_PLL_CML_ENABLE
> clock gate.
s/cml/CML/
In addition to Jerome's feedback - it would also be helpful to explain
when CML outputs should be enabled, i.e. which platforms and why those
ones?
>
> This clock gate is optional, so do not fail if it is missing in the
> devicetree.
If certain platforms require PCIE_PLL_CML_ENABLE to work reliably and
thus the clock is specified in the device tree - then surely if there
is an error in enabling the clock we should fail? I.e. should you only
ignore -ENOENT here?
Thanks,
Andrew Murray
>
> Signed-off-by: Remi Pommarel <repk@xxxxxxxxxxxx>
> ---
> drivers/pci/controller/dwc/pci-meson.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
> index 3772b02a5c55..32b70ea9a426 100644
> --- a/drivers/pci/controller/dwc/pci-meson.c
> +++ b/drivers/pci/controller/dwc/pci-meson.c
> @@ -89,6 +89,7 @@ struct meson_pcie_clk_res {
> struct clk *mipi_gate;
> struct clk *port_clk;
> struct clk *general_clk;
> + struct clk *pll_cml_gate;
> };
>
> struct meson_pcie_rc_reset {
> @@ -300,6 +301,10 @@ static int meson_pcie_probe_clocks(struct meson_pcie *mp)
> if (IS_ERR(res->clk))
> return PTR_ERR(res->clk);
>
> + res->pll_cml_gate = meson_pcie_probe_clock(dev, "pll_cml_en", 0);
> + if (IS_ERR(res->pll_cml_gate))
> + res->pll_cml_gate = NULL;
> +
> return 0;
> }
>
> --
> 2.24.0
>
