PCIe device probing failures have been seen on some AXG platforms and were
due to unreliable clock signal output. Setting HHI_MIPI_CNTL0[26] bit
solved the problem. After being contacted about this, vendor reported that
this bit was linked to PCIe PLL CML output.
This serie adds a way to set this bit through AXG clock gating logic.
Platforms having this kind of issue could make use of this gating by
applying a patch to their devicetree similar to:
clocks = <&clkc CLKID_USB
&clkc CLKID_MIPI_ENABLE
&clkc CLKID_PCIE_A
- &clkc CLKID_PCIE_CML_EN0>;
+ &clkc CLKID_PCIE_CML_EN0
+ &clkc CLKID_PCIE_PLL_CML_ENABLE>;
clock-names = "pcie_general",
"pcie_mipi_en",
"pcie",
- "port";
+ "port",
+ "pll_cml_en";
resets = <&reset RESET_PCIE_PHY>,
<&reset RESET_PCIE_A>,
<&reset RESET_PCIE_APB>;
Remi Pommarel (2):
clk: meson: axg: add pcie pll cml gating
PCI: amlogic: Use PCIe pll gate when available
drivers/clk/meson/axg.c | 3 +++
drivers/clk/meson/axg.h | 2 +-
drivers/pci/controller/dwc/pci-meson.c | 5 +++++
include/dt-bindings/clock/axg-clkc.h | 1 +
4 files changed, 10 insertions(+), 1 deletion(-)
--
2.24.0
