Hi Remi, On Sun, Dec 8, 2019 at 9:56 PM Remi Pommarel <repk@xxxxxxxxxxxx> wrote: [...] > +static MESON_GATE(axg_pcie_pll_cml_enable, HHI_MIPI_CNTL0, 26); we already have CLKID_PCIE_CML_EN0 do you know how this new one is related (in terms of clock hierarchy) to the existing one? [...] > --- a/include/dt-bindings/clock/axg-clkc.h > +++ b/include/dt-bindings/clock/axg-clkc.h > @@ -72,5 +72,6 @@ > #define CLKID_PCIE_CML_EN1 80 > #define CLKID_MIPI_ENABLE 81 > #define CLKID_GEN_CLK 84 > +#define CLKID_PCIE_PLL_CML_ENABLE 91 this has to be a separate patch if you want the .dts patch to go into the same cycle the .dts change depends on this one. what we typically do is to apply the dt-bindings patches to a separate clock branch, create an immutable tag and then Kevin pulls that into his dt64 branch. the clock controller changes go into a separate patch in the clk-meson/drivers branch to avoid conflicts with other driver changes Martin
