On Wed, Nov 06, 2019 at 11:44:01AM +0800, Dilip Kota wrote: > Add YAML schemas for PCIe RC controller on Intel Gateway SoCs > which is Synopsys DesignWare based PCIe core. > > Signed-off-by: Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx> > Reviewed-by: Andrew Murray <andrew.murray@xxxxxxx> > --- > Changes on v5: > Add Reviewed-by Andrew Murray. > Add possible values and default value for max-link-speed. > Remove $ref and add maximum and default for reset-assert-ms. > Set true flag for linux,pci-domain. > Define maxItems for ranges and clock. > Define maximum for num-lanes. > Update required list: > Add #address-cells, #size-cells, #interrupt-cells. > Remove num-lanes and linux,pci-domain. > Add required header files in example. > Remove status entry in example. > > changes on v4: > Add "snps,dw-pcie" compatible. > Rename phy-names property value to pcie. > And maximum and minimum values to num-lanes. > Add ref for reset-assert-ms entry and update the > description for easy understanding. > Remove PCIe core interrupt entry. > > changes on v3: > Add the appropriate License-Identifier > Rename intel,rst-interval to 'reset-assert-us' > Add additionalProperties: false > Rename phy-names to 'pciephy' > Remove the dtsi node split of SoC and board in the example > Add #interrupt-cells = <1>; or else interrupt parsing will fail > Name yaml file with compatible name > > .../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 +++++++++++++++++++++ > 1 file changed, 138 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml I'm working on a common PCI schema which will shrink this, but in the meantime: Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
