Intel PCIe is Synopsys based controller utilizes the DesignWare framework for host initialization and Intel application specific register configurations. Changes on v5: Add Reviewed-by: Andrew Murray for device tree YAML schema patch. Address patchv4 review comments. Sysfs patch work in progress, so not submitted in this patch revision. Add changes in artpec6 PCI driver to call dw helper function for programming FTS. Dilip Kota (3): dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller dwc: PCI: intel: PCIe RC controller driver PCI: artpec6: Configure FTS with dwc helper function .../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 ++++++ drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-artpec6.c | 8 +- drivers/pci/controller/dwc/pcie-designware.c | 57 +++ drivers/pci/controller/dwc/pcie-designware.h | 12 + drivers/pci/controller/dwc/pcie-intel-gw.c | 538 ++++++++++++++++ include/uapi/linux/pci_regs.h | 1 + 8 files changed, 758 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.c -- 2.11.0
