Hi Kishon On Fri, Oct 11, 2019 at 8:35 AM Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > Hi Kishon, > > On Thu, Oct 10, 2019 at 12:32 PM Kishon Vijay Abraham I <kishon@xxxxxx> wrote: > > > > Hi Prabhakar, > > > > On 10/10/19 4:57 PM, Lad, Prabhakar wrote: > > > Hello, > > > > > > I am currently working on adding pcie-endpoint support for a > > > controller, this controller doesn't support outbound- inbound address > > > translations, it has 1-1 mapping between the CPU and PCI addresses, > > > the current endpoint framework is based on outbound-inbound > > > translations, what is the best approach to add this support, or is > > > there any WIP already for it ? > > > > How will the endpoint access host buffer without outbound ATU? I assume the PCI > > address reserved for endpoint is not the full 32-bit or 64-bit address space? > > In that case, the endpoint cannot directly access the host buffer (unless the > > host already knows the address space of the endpoint and gives the endpoint an > > address in its OB address space). > > I lied in my previous mail. a] The controller needs the cpu_address before starting the link, ie with the current implementation,the bars physical address in endpoint are assigned using dma_alloc_coherent(), but I what I actually want here is the phys_addr returned by pci_epc_mem_alloc_addr(). b] In the pci_endpoint_test driver, the pci_address sent to the endpoint driver is again dma_alloc_coherent(), but the address which I actually want to send to endpoint is the BAR's assigned regions in the RC. Cheers, --Prabhakar
