On Fri, Aug 09, 2019 at 10:15:56AM +0530, Vidya Sagar wrote: > Tegra194 has six PCIe controllers based on Synopsys DesignWare core. > There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO: > Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively. > Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses > UPHY lanes from NVHS brick. Lane mapping in HSIO UPHY brick to each PCIe > controller (0~4) is controlled in XBAR module by BPMP-FW. Since PCIe > core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is used > to connect each UPHY lane (applicable to both HSIO and NVHS UPHY bricks) > to PCIe controller > This patch series > - Adds support for P2U PHY driver > - Adds support for PCIe host controller > - Adds device tree nodes each PCIe controllers > - Enables nodes applicable to p2972-0000 platform > - Adds helper APIs in Designware core driver to get capability regs offset > - Adds defines for new feature registers of PCIe spec revision 4 > - Makes changes in DesignWare core driver to get Tegra194 PCIe working > > Testing done on P2972-0000 platform > - Able to get PCIe link up with on-board Marvel eSATA controller > - Able to get PCIe link up with NVMe cards connected to M.2 Key-M slot > - Able to do data transfers with both SATA drives and NVMe cards > - Able to perform suspend-resume sequence Do you happen to have a patch for P2972-0000 PCI support? I don't see it in this series. Thierry
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