On Fri, Aug 09, 2019 at 10:16:08AM +0530, Vidya Sagar wrote: > Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface > with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module. > For each PCIe lane of a controller, there is a P2U unit instantiated at > hardware level. This driver provides support for the programming required > for each P2U that is going to be used for a PCIe controller. > > Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx> > Acked-by: Kishon Vijay Abraham I <kishon@xxxxxx> > --- > V15: > * None > > V14: > * None > > V13: > * None > > V12: > * None > > V11: > * Replaced PTR_ERR_OR_ZERO() with PTR_ERR() as the check for zero is already > present in the code. > > V10: > * Used _relaxed() versions of readl() & writel() > > V9: > * Made it dependent on ARCH_TEGRA_194_SOC directly instead of ARCH_TEGRA > > V8: > * Changed P2U driver file name from pcie-p2u-tegra194.c to phy-tegra194-p2u.c > > V7: > * None > > V6: > * Addressed review comments from Thierry > > V5: > * None > > V4: > * Rebased on top of linux-next top of the tree > > V3: > * Replaced spaces with tabs in Kconfig file > * Sorted header file inclusion alphabetically > > V2: > * Added COMPILE_TEST in Kconfig > * Removed empty phy_ops implementations > * Modified code according to DT documentation file modifications > > drivers/phy/tegra/Kconfig | 7 ++ > drivers/phy/tegra/Makefile | 1 + > drivers/phy/tegra/phy-tegra194-p2u.c | 120 +++++++++++++++++++++++++++ > 3 files changed, 128 insertions(+) > create mode 100644 drivers/phy/tegra/phy-tegra194-p2u.c Acked-by: Thierry Reding <treding@xxxxxxxxxx>
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