On 1/24/2019 4:43 PM, Bolen, Austin wrote: > On 1/23/2019 1:02 PM, Lukas Wunner wrote: >> > > <snip> > >> >> Well, usually it's desirable to bring up the slot as quickly as possible, >> so once we get any kind of link or presence event, we immediately try to >> bring up the slot. >> >> We do allow a 20 + 100 ms delay in pcie_wait_for_link() between link up >> and presence detect up, just not 400 ms. > > Is the hot-inserted device's config space accessed immediately after > waiting this 20 + 100 ms delay? Per PCIe spec, in Gen 3 mode, software > should wait at least (1s - CTO value) after Data Link Layer Link Active > before accessing config space. The exception is if OS enables CRS > Software Visibility in which case config space can be accessed 100 ms > after Data Link Layer Link Active. Is CRS Software Visibility being used? > I forgot... Readiness Notifications can also let software bypass these first access times but I've not seen anybody implement RN so assume it is not being used here. > Cheers, > Austin > >> >> Thanks, >> >> Lukas >> > >
