Hello Luis,
Sorry for the long delay, the Christmas/New Year vacation and some
personal issues got in the way.
On Tue, 18 Dec 2018 23:13:59 +0000, Luís Mendes wrote:
> The complete lspci outputs follow in attachments.
>
> In the working case, region 5, is at e0200000 with size 256k and is
> immediately followed by the expansion rom at e0240000 [disabled]
> [size=128K], however in the non-working case,
> region 5 has a completely different address, and regions are not contiguous.
> Another difference is at:
> Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
> Address: 00000000f1020a04 Data: 0f12
>
> vs
>
> Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
> Address: 0000000000000000 Data: 0000
>
> So it looks like MSI is not being enabled with the new PCI management
> code and looks like the PCI rom maybe mapped to an invalid memory
> address, causing the ioremap to fail.
Could you apply the patches attached (one is meant to be used with 4.20
as-is, and the other meant to be used with 4.20 +
1f08673eef1236f7d02d93fcf596bb8531ef0d12 reverted), and post the
complete boot logs ?
You will most likely have to increase CONFIG_LOG_BUF_SHIFT to avoid
having dropped messages, as my additional debug messages are quite
verbose. I'm using CONFIG_LOG_BUF_SHIFT=16.
Having these boot lots will help me investigate the issue.
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
>From 2bd51f2891150b524f73e58c55da5fe68a7d1457 Mon Sep 17 00:00:00 2001
From: Thomas Petazzoni <thomas.petazzoni@xxxxxxxxxxx>
Date: Tue, 8 Jan 2019 10:59:19 +0100
Subject: [PATCH] PCI: mvebu: add debug
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@xxxxxxxxxxx>
---
drivers/pci/controller/pci-mvebu.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index fa0fc46edb0c..9715ba070263 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -624,9 +624,13 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
return PCIBIOS_DEVICE_NOT_FOUND;
/* Access the emulated PCI-to-PCI bridge */
- if (bus->number == 0)
+ if (bus->number == 0) {
+ dev_info(&pcie->pdev->dev,
+ "%s: devfn=0x%x, where=0x%x, size=%d, val=0x%x\n",
+ __func__, devfn, where, size, val);
return pci_bridge_emul_conf_write(&port->bridge, where,
size, val);
+ }
if (!mvebu_pcie_link_up(port))
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -653,9 +657,14 @@ static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
}
/* Access the emulated PCI-to-PCI bridge */
- if (bus->number == 0)
- return pci_bridge_emul_conf_read(&port->bridge, where,
- size, val);
+ if (bus->number == 0) {
+ ret = pci_bridge_emul_conf_read(&port->bridge, where,
+ size, val);
+ dev_info(&pcie->pdev->dev,
+ "%s: devfn=0x%x, where=0x%x, size=%d, val=0x%x\n",
+ __func__, devfn, where, size, *val);
+ return ret;
+ }
if (!mvebu_pcie_link_up(port)) {
*val = 0xffffffff;
@@ -986,6 +995,8 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
/* Get the PCIe IO aperture */
mvebu_mbus_get_pcie_io_aperture(&pcie->io);
+ dev_info(dev, "MEM: %pR, IO: %pR\n", &pcie->mem, &pcie->io);
+
if (resource_size(&pcie->io) != 0) {
pcie->realio.flags = pcie->io.flags;
pcie->realio.start = PCIBIOS_MIN_IO;
--
2.20.1
>From ac0aa231c23390150dddfdf923400af2a4a4e86b Mon Sep 17 00:00:00 2001
From: Thomas Petazzoni <thomas.petazzoni@xxxxxxxxxxx>
Date: Tue, 8 Jan 2019 10:59:19 +0100
Subject: [PATCH] PCI: mvebu: add debug
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@xxxxxxxxxxx>
---
drivers/pci/controller/pci-mvebu.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index dacad51f19e7..94aa7e42c5e2 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -796,8 +796,12 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
return PCIBIOS_DEVICE_NOT_FOUND;
/* Access the emulated PCI-to-PCI bridge */
- if (bus->number == 0)
+ if (bus->number == 0) {
+ dev_info(&pcie->pdev->dev,
+ "%s: devfn=0x%x, where=0x%x, size=%d, val=0x%x\n",
+ __func__, devfn, where, size, val);
return mvebu_sw_pci_bridge_write(port, where, size, val);
+ }
if (!mvebu_pcie_link_up(port))
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -824,8 +828,13 @@ static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
}
/* Access the emulated PCI-to-PCI bridge */
- if (bus->number == 0)
- return mvebu_sw_pci_bridge_read(port, where, size, val);
+ if (bus->number == 0) {
+ ret = mvebu_sw_pci_bridge_read(port, where, size, val);
+ dev_info(&pcie->pdev->dev,
+ "%s: devfn=0x%x, where=0x%x, size=%d, val=0x%x\n",
+ __func__, devfn, where, size, *val);
+ return ret;
+ }
if (!mvebu_pcie_link_up(port)) {
*val = 0xffffffff;
@@ -1156,6 +1165,8 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
/* Get the PCIe IO aperture */
mvebu_mbus_get_pcie_io_aperture(&pcie->io);
+ dev_info(dev, "MEM: %pR, IO: %pR\n", &pcie->mem, &pcie->io);
+
if (resource_size(&pcie->io) != 0) {
pcie->realio.flags = pcie->io.flags;
pcie->realio.start = PCIBIOS_MIN_IO;
--
2.20.1
