On Tue, Nov 27, 2018 at 02:22:48PM -0800, Sagi Grimberg wrote: > Hi, > > During a rescan process, pci bridge regions capabilities are > re-verified. In particular, prefetchable regions are checked for 64-bit > addressing support. This check is done by reading the base-address > register 4 LSBs. > > Then, we "double check" that the bridge support 64-bit prefetchable > addresses. This double-check is done by writing ones to the base-address > buffer (high 32-bit), and check if we read zeros [1]. > > Questions: > 1. Why do we need to "double-check"? > 2. What is expected to happen if a memory transaction arrive to this > port during this process, while its base-address is miss-configured? > (say, a read-transaction issued by a peer device) I think has something to do with how pbus_size_mem() assumes a 64-bit window will not have a 32-bit resource. If a bridge has a prefetchable window, but happens to contain an address < 4GB, we clear the IORESOURCE_MEM_64 flag so that it can get a resource.
