Questions about pci_bridge_check_ranges()

[Sagi Grimberg <sagi@xxxxxxxxxxx>]

Hi,

During a rescan process, pci bridge regions capabilities are
re-verified. In particular, prefetchable regions are checked for 64-bit
addressing support. This check is done by reading the base-address
register 4 LSBs.

Then, we "double check" that the bridge support 64-bit prefetchable
addresses. This double-check is done by writing ones to the base-address
buffer (high 32-bit), and check if we read zeros [1].

Questions:
1. Why do we need to "double-check"?
2. What is expected to happen if a memory transaction arrive to this
   port during this process, while its base-address is miss-configured?
   (say, a read-transaction issued by a peer device)

[1] (drivers/pci/setup-bus.c:780):
/* double check if bridge does support 64 bit pref */
if (b_res[2].flags & IORESOURCE_MEM_64) {
	u32 mem_base_hi, tmp;
	pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
				 &mem_base_hi);
	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
			       0xffffffff);
	pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp)
	if (!tmp)
		b_res[2].flags &= ~IORESOURCE_MEM_64;
	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
			       mem_base_hi);
}

Cheers,
Sagi.