Hi, I have following queries w.r.t PCIe endpoint framework in kernel in the context of a DesignWare core IP. -> Since the PCIe spec says that the endpoint should have stable REFCLK before it observes PEX_RST from host, endpoint's LTSSM in a way depends on arrival of PEX_RST from host (there by locking endpoint's internal PLLs to incoming REFCLK from host, followed by core programming and finally enabling LTSSM of endpoint). But, IIUC, the endpoint framework starts LTSSM based on writing '1' to 'start' in epc device's config-fs entry. What is the rationale behind it? Why is starting LTSSM in endpoint decoupled from PEX_RST toggle? -> Also, kernel documentation says that the sequence is first creating EPF device followed by EPC device and linking it with already created EPF device and finally going for link up. This implicitly assumes that, programming of core registers is happening in the absence of REFCLK from host. Does it mean, there are internal clock sources available for DWC core programming (dbi registers programming) before REFCLK is available from host, and, finally when PEX_RST is observed, switch clock source from internal clock source to external REFCLK? Thanks, Vidya Sagar
