On 8/31/2018 2:26 PM, Keith Busch wrote:
This is safe because the pciehp and DPC drivers share the same interrupt. The DPC driver sets the bus state in the top-half interrupt context, and the pciehp driver checks and masks off link events in its bottom-half error handler.
Where is this coming from? Is there a spec reference? DPC and HP interrupts can be implemented as MSI-x interrupts and could be unrelated interrupt IDs?
