On Sun, Aug 05, 2018 at 01:02:58PM -0700, Wesley Terpstra wrote: > FYI, This Xilinx PCIe IP 32-bit cap only applies to SOME instances of > the IP. The Ultrascale+ version of Xilinx PCIe hard IP does support > 64-bit or 32-bit. The Virtex7 version only supports 32-bit. The > pcie-xilinx driver woks with both of these root complexes. So probably > there should be a conditional hook in the DTS that triggers the > work-around behaviour. Either we'll need to able to detect which version we use based on registrs, or we will indeed need firmware information. Note that we already have the mechanism for firmware directed dma limits in place, it is called the dma-ranges DT property. If we can get the SiFive firmware to set it up properly the RISC-V swiotlb code will just do the right thing.
