This PCIe bridge only has a 32 bit bus master interface, thus truncating
the DMA capability of all PCIe devices attached beneath it. This caps
the child device capability so that these devices work on systems with
physical memory beyond the 4GiB threshold.
Based on an earlier patch from Wesley W. Terpstra <wesley@xxxxxxxxxx>.
Signed-off-by: Christoph Hellwig <hch@xxxxxx>
---
drivers/pci/controller/pcie-xilinx.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/pcie-xilinx.c
index 7b1389d8e2a5..ccfd91e0515f 100644
--- a/drivers/pci/controller/pcie-xilinx.c
+++ b/drivers/pci/controller/pcie-xilinx.c
@@ -197,6 +197,16 @@ static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
return port->reg_base + relbus + where;
}
+/*
+ * This PCIe bridge only has a 32 bit bus master interface, thus truncating
+ * the DMA capability of all PCIe devices attached beneath it.
+ */
+static int xilinx_pcie_add_device(struct pci_dev *pdev)
+{
+ pdev->dev.bus_dma_mask = DMA_BIT_MASK(32);
+ return 0;
+}
+
/* PCIe operations */
static struct pci_ops xilinx_pcie_ops = {
.map_bus = xilinx_pcie_map_bus,
@@ -665,6 +675,7 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
bridge->ops = &xilinx_pcie_ops;
bridge->map_irq = of_irq_parse_and_map_pci;
bridge->swizzle_irq = pci_common_swizzle;
+ bridge->add_device = xilinx_pcie_add_device;
#ifdef CONFIG_PCI_MSI
xilinx_pcie_msi_chip.dev = dev;
--
2.18.0
