tree: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/misc head: 68e3ce09cb93f1a470b19816fa254b69480f246a commit: 68e3ce09cb93f1a470b19816fa254b69480f246a [2/2] IB/hfi1: Replace custom hfi1 macros with PCIe macros config: x86_64-randconfig-x001-201816 (attached as .config) compiler: gcc-7 (Debian 7.3.0-16) 7.3.0 reproduce: git checkout 68e3ce09cb93f1a470b19816fa254b69480f246a # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): drivers/infiniband//hw/hfi1/pcie.c: In function 'extract_speed': >> drivers/infiniband//hw/hfi1/pcie.c:263:7: error: 'PCI_EXP_LNKSTA_CLS_8_0GT' undeclared (first use in this function); did you mean 'PCI_EXP_LNKSTA_CLS_8_0GB'? case PCI_EXP_LNKSTA_CLS_8_0GT: ^~~~~~~~~~~~~~~~~~~~~~~~ PCI_EXP_LNKSTA_CLS_8_0GB drivers/infiniband//hw/hfi1/pcie.c:263:7: note: each undeclared identifier is reported only once for each function it appears in drivers/infiniband//hw/hfi1/pcie.c: In function 'pcie_speeds': >> drivers/infiniband//hw/hfi1/pcie.c:318:40: error: 'PCI_EXP_LNKCAP_SLS_8_0GT' undeclared (first use in this function); did you mean 'PCI_EXP_LNKCAP_SLS_8_0GB'? if ((linkcap & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_8_0GT) { ^~~~~~~~~~~~~~~~~~~~~~~~ PCI_EXP_LNKCAP_SLS_8_0GB vim +263 drivers/infiniband//hw/hfi1/pcie.c 249 250 /* return the PCIe link speed from the given link status */ 251 static u32 extract_speed(u16 linkstat) 252 { 253 u32 speed; 254 255 switch (linkstat & PCI_EXP_LNKSTA_CLS) { 256 default: /* not defined, assume Gen1 */ 257 case PCI_EXP_LNKSTA_CLS_2_5GB: 258 speed = 2500; /* Gen 1, 2.5GHz */ 259 break; 260 case PCI_EXP_LNKSTA_CLS_5_0GB: 261 speed = 5000; /* Gen 2, 5GHz */ 262 break; > 263 case PCI_EXP_LNKSTA_CLS_8_0GT: 264 speed = 8000; /* Gen 3, 8GHz */ 265 break; 266 } 267 return speed; 268 } 269 270 /* return the PCIe link speed from the given link status */ 271 static u32 extract_width(u16 linkstat) 272 { 273 return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; 274 } 275 276 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */ 277 static void update_lbus_info(struct hfi1_devdata *dd) 278 { 279 u16 linkstat; 280 int ret; 281 282 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); 283 if (ret) { 284 dd_dev_err(dd, "Unable to read from PCI config\n"); 285 return; 286 } 287 288 dd->lbus_width = extract_width(linkstat); 289 dd->lbus_speed = extract_speed(linkstat); 290 snprintf(dd->lbus_info, sizeof(dd->lbus_info), 291 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); 292 } 293 294 /* 295 * Read in the current PCIe link width and speed. Find if the link is 296 * Gen3 capable. 297 */ 298 int pcie_speeds(struct hfi1_devdata *dd) 299 { 300 u32 linkcap; 301 struct pci_dev *parent = dd->pcidev->bus->self; 302 int ret; 303 304 if (!pci_is_pcie(dd->pcidev)) { 305 dd_dev_err(dd, "Can't find PCI Express capability!\n"); 306 return -EINVAL; 307 } 308 309 /* find if our max speed is Gen3 and parent supports Gen3 speeds */ 310 dd->link_gen3_capable = 1; 311 312 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); 313 if (ret) { 314 dd_dev_err(dd, "Unable to read from PCI config\n"); 315 return ret; 316 } 317 > 318 if ((linkcap & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_8_0GT) { 319 dd_dev_info(dd, 320 "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n", 321 linkcap & PCI_EXP_LNKCAP_SLS); 322 dd->link_gen3_capable = 0; 323 } 324 325 /* 326 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed 327 */ 328 if (parent && dd->pcidev->bus->max_bus_speed != PCIE_SPEED_8_0GT) { 329 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); 330 dd->link_gen3_capable = 0; 331 } 332 333 /* obtain the link width and current speed */ 334 update_lbus_info(dd); 335 336 dd_dev_info(dd, "%s\n", dd->lbus_info); 337 338 return 0; 339 } 340 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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