tree: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next head: 36e218fd55522ccfd4463fbf57909353e58280bd commit: 25210702e2122f42f6b2f44e0446e819d44bf113 [34/50] PCI/IOV: Use VF0 cached config registers for other VFs config: x86_64-randconfig-x017-201809 (attached as .config) compiler: gcc-7 (Debian 7.3.0-1) 7.3.0 reproduce: git checkout 25210702e2122f42f6b2f44e0446e819d44bf113 # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): drivers/pci/probe.c: In function 'pci_setup_device': >> drivers/pci/probe.c:1465:19: error: 'struct pci_dev' has no member named 'physfn'; did you mean 'is_physfn'? hdr_type = dev->physfn->sriov->hdr_type; ^~~~~~ is_physfn drivers/pci/probe.c:1490:16: error: 'struct pci_dev' has no member named 'physfn'; did you mean 'is_physfn'? class = dev->physfn->sriov->class; ^~~~~~ is_physfn drivers/pci/probe.c:1533:33: error: 'struct pci_dev' has no member named 'physfn'; did you mean 'is_physfn'? dev->subsystem_vendor = dev->physfn->sriov->subsystem_vendor; ^~~~~~ is_physfn drivers/pci/probe.c:1534:33: error: 'struct pci_dev' has no member named 'physfn'; did you mean 'is_physfn'? dev->subsystem_device = dev->physfn->sriov->subsystem_device; ^~~~~~ is_physfn vim +1465 drivers/pci/probe.c 1444 1445 /** 1446 * pci_setup_device - Fill in class and map information of a device 1447 * @dev: the device structure to fill 1448 * 1449 * Initialize the device structure with information about the device's 1450 * vendor,class,memory and IO-space addresses, IRQ lines etc. 1451 * Called at initialisation of the PCI subsystem and by CardBus services. 1452 * Returns 0 on success and negative if unknown type of device (not normal, 1453 * bridge or CardBus). 1454 */ 1455 int pci_setup_device(struct pci_dev *dev) 1456 { 1457 u32 class; 1458 u16 cmd; 1459 u8 hdr_type; 1460 int pos = 0; 1461 struct pci_bus_region region; 1462 struct resource *res; 1463 1464 if (dev->is_virtfn) > 1465 hdr_type = dev->physfn->sriov->hdr_type; 1466 else if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) 1467 return -EIO; 1468 1469 dev->sysdata = dev->bus->sysdata; 1470 dev->dev.parent = dev->bus->bridge; 1471 dev->dev.bus = &pci_bus_type; 1472 dev->hdr_type = hdr_type & 0x7f; 1473 dev->multifunction = !!(hdr_type & 0x80); 1474 dev->error_state = pci_channel_io_normal; 1475 set_pcie_port_type(dev); 1476 1477 pci_dev_assign_slot(dev); 1478 1479 /* 1480 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1481 * set this higher, assuming the system even supports it. 1482 */ 1483 dev->dma_mask = 0xffffffff; 1484 1485 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1486 dev->bus->number, PCI_SLOT(dev->devfn), 1487 PCI_FUNC(dev->devfn)); 1488 1489 if (dev->is_virtfn) 1490 class = dev->physfn->sriov->class; 1491 else 1492 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1493 dev->revision = class & 0xff; 1494 dev->class = class >> 8; /* upper 3 bytes */ 1495 1496 pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n", 1497 dev->vendor, dev->device, dev->hdr_type, dev->class); 1498 1499 /* Need to have dev->class ready */ 1500 dev->cfg_size = pci_cfg_space_size(dev); 1501 1502 /* Need to have dev->cfg_size ready */ 1503 set_pcie_thunderbolt(dev); 1504 1505 /* "Unknown power state" */ 1506 dev->current_state = PCI_UNKNOWN; 1507 1508 /* Early fixups, before probing the BARs */ 1509 pci_fixup_device(pci_fixup_early, dev); 1510 1511 /* Device class may be changed after fixup */ 1512 class = dev->class >> 8; 1513 1514 if (dev->non_compliant_bars) { 1515 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1516 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 1517 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 1518 cmd &= ~PCI_COMMAND_IO; 1519 cmd &= ~PCI_COMMAND_MEMORY; 1520 pci_write_config_word(dev, PCI_COMMAND, cmd); 1521 } 1522 } 1523 1524 dev->broken_intx_masking = pci_intx_mask_broken(dev); 1525 1526 switch (dev->hdr_type) { /* header type */ 1527 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 1528 if (class == PCI_CLASS_BRIDGE_PCI) 1529 goto bad; 1530 pci_read_irq(dev); 1531 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); 1532 if (dev->is_virtfn) { 1533 dev->subsystem_vendor = dev->physfn->sriov->subsystem_vendor; 1534 dev->subsystem_device = dev->physfn->sriov->subsystem_device; 1535 } else { 1536 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1537 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); 1538 } 1539 1540 /* 1541 * Do the ugly legacy mode stuff here rather than broken chip 1542 * quirk code. Legacy mode ATA controllers have fixed 1543 * addresses. These are not always echoed in BAR0-3, and 1544 * BAR0-3 in a few cases contain junk! 1545 */ 1546 if (class == PCI_CLASS_STORAGE_IDE) { 1547 u8 progif; 1548 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1549 if ((progif & 1) == 0) { 1550 region.start = 0x1F0; 1551 region.end = 0x1F7; 1552 res = &dev->resource[0]; 1553 res->flags = LEGACY_IO_RESOURCE; 1554 pcibios_bus_to_resource(dev->bus, res, ®ion); 1555 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", 1556 res); 1557 region.start = 0x3F6; 1558 region.end = 0x3F6; 1559 res = &dev->resource[1]; 1560 res->flags = LEGACY_IO_RESOURCE; 1561 pcibios_bus_to_resource(dev->bus, res, ®ion); 1562 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", 1563 res); 1564 } 1565 if ((progif & 4) == 0) { 1566 region.start = 0x170; 1567 region.end = 0x177; 1568 res = &dev->resource[2]; 1569 res->flags = LEGACY_IO_RESOURCE; 1570 pcibios_bus_to_resource(dev->bus, res, ®ion); 1571 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", 1572 res); 1573 region.start = 0x376; 1574 region.end = 0x376; 1575 res = &dev->resource[3]; 1576 res->flags = LEGACY_IO_RESOURCE; 1577 pcibios_bus_to_resource(dev->bus, res, ®ion); 1578 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", 1579 res); 1580 } 1581 } 1582 break; 1583 1584 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 1585 if (class != PCI_CLASS_BRIDGE_PCI) 1586 goto bad; 1587 1588 /* 1589 * The PCI-to-PCI bridge spec requires that subtractive 1590 * decoding (i.e. transparent) bridge must have programming 1591 * interface code of 0x01. 1592 */ 1593 pci_read_irq(dev); 1594 dev->transparent = ((dev->class & 0xff) == 1); 1595 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 1596 set_pcie_hotplug_bridge(dev); 1597 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 1598 if (pos) { 1599 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 1600 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 1601 } 1602 break; 1603 1604 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 1605 if (class != PCI_CLASS_BRIDGE_CARDBUS) 1606 goto bad; 1607 pci_read_irq(dev); 1608 pci_read_bases(dev, 1, 0); 1609 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 1610 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 1611 break; 1612 1613 default: /* unknown header */ 1614 pci_err(dev, "unknown header type %02x, ignoring device\n", 1615 dev->hdr_type); 1616 return -EIO; 1617 1618 bad: 1619 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 1620 dev->class, dev->hdr_type); 1621 dev->class = PCI_CLASS_NOT_DEFINED << 8; 1622 } 1623 1624 /* We found a fine healthy device, go go go... */ 1625 return 0; 1626 } 1627 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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