Hi Pratyush, Thank you very much for the comments. Please see below. Best Regards, Victor Gu From: Pratyush Anand [mailto:pratyush.anand@xxxxxxxxx] Sent: 2018年1月30日 15:21 To: Victor Gu <xigu@xxxxxxxxxxx>; Kishon Vijay Abraham I <kishon@xxxxxx>; Joao Pinto <Joao.Pinto@xxxxxxxxxxxx> Cc: jingoohan1@xxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; Nadav Haklai <nadavh@xxxxxxxxxxx>; Wilson Ding <dingwei@xxxxxxxxxxx>; Thomas Petazzoni <thomas.petazzoni@xxxxxxxxxxxxxxxxxx> Subject: Re: Designware 64bit PCIe bus address support + Kishon, Joao On Tue, Jan 30, 2018 at 11:36 AM, Victor Gu <xigu@xxxxxxxxxxx> wrote: Hi Jingoo and Pratyush, I am Victor Gu, SW RD from Marvell. During the testing we found the designware PCIe works well with 64 bit CPU address and 32 bit PCIe bus address(translated by ATU). But cannot access the PCIe EP if both of them use the 64 bit CPU address, such as 0x800000000. You mean that you want to keep PCIe bus address (ATU translated address) as 64 bit? If yes, that should be doable. But, bus address always depends on the bus, device and function address of EP that you want to target. I mean the ECAM(memory mapped access from host CPU to PCIe EP device), not the PIO by bus/device/function. The PCIe host will define the memory range used for BAR allocation, after BAR allocation the host CPU can use the CPU address in the memory range to access the PCIe EP. We tested two cases on our designware based SoC with the PCIe EP which supports 64bit BARs 1. 64bit(value > 32bit) CPU address map to 64bit(value > 32bit) PCI bus address: <0x82000000 0x8 0x00000000 0x8 0x00000000 0x1 0x0>; In this case, the memory resource starts from CPU address 0x800000000, and PCIe bus address 0x800000000, size is 0x100000000 The CPU gets nothing when access CPU address 0x800000000 2. 64bit(value > 32bit) CPU address map to 32bit(value < 32bit) PCI bus address: <0x82000000 0x0 0x00000000 0x8 0x00000000 0x1 0x0>; In this case, the memory resources still starts from CPU address 0x800000000, but the PCIe bus address start from 0x0, the designware ATU will translate the CPU address to PCIe bus address. The CPU can get the correct values when access CPU address 0x800000000 after the BAR allocation. Do you know if the designware PCIe IP supports 64 bit PCIe bus address? And if the designware PCIe Linux driver supports 64 bit PCIe bus address? I think, they should work. Kishon and Joao can give better comments. Hi Kishon and Joao, any idea about the above issue? Is there any designware PCIe based SoC can support the 64 bit(value > 32bit) bus address? Thank you for the help! Best Regards, Victor Gu @Kishon, @Joao, Hi Guys would you like to take over Maintaniership of the driver. I do not have synopsys platform, and moreover I am doing something else for quite some time now.
