On Tue, Jan 23, 2018 at 05:04:22PM -0800, Linus Torvalds wrote:
> On Tue, Jan 23, 2018 at 4:46 PM, Bjorn Helgaas <helgaas@xxxxxxxxxx> wrote:
> > On Tue, Jan 23, 2018 at 12:49:22PM -0800, Linus Torvalds wrote:
> >>
> >> I suspect you're editing your mailbox, or you're using some broken
> >> mailer setup, or something (using some broken "export" function?),
> >> because you're corrupting Christian's name all the time:
> >
> > I'm not editing my mailbox, but I am using stgit. The "From:" header
> > uses encoded-word syntax for Christian's name, and I think stgit is
> > not decoding that when applying the patch.
>
> Ahh. Ok, that would explain it.
>
> > When I save the patch email message from mutt (or gmail, for that
> > matter), I see:
> >
> > From: "=?UTF-8?q?Christian=20K=C3=B6nig?=" ...
>
> Yes. That's the standard locale encoding format for header values
> (mainly subject and author), since the
>
> Content-Type: text/plain; charset=utf-8
>
> only applies to the *body* of the email.
>
> So then the email handling tools have to handle that correctly, and as
> you noticed, "git am" does so:
>
> > Applying that patch with "git am" results in the correct
> >
> > Author: Christian König <ckoenig.leichtzumerken@xxxxxxxxx
>
> But apparently stgit does not:
>
> > Applying the identical patch with "stg import -M" results in
> >
> > Author: =?UTF-8?q?Christian=20K=C3=B6nig?= <ckoenig.leichtzumerken@xxxxxxxxx>
>
> I'm adding Peter Grayson and Catalin Marinas to the participants,
> since they seem to be the main stgit developers.
>
> Presumably there is either a flag for this (which should presumably be
> the default). Or if not, maybe stgit can just be fixed?
>
> [ I go off looking at the stgit sources. ]
>
> Oddly, stgit seems to even have a *testcase* for this:
>
> - t/t1800-import/email-qp:
>
> From: Inge =?utf-8?q?Str=C3=B6m?= <inge@xxxxxxxxx>
>
> and that test-case harkens back to 2006. I wonder why it doesn't seem
> to work for you and Christian.
>
> Bjorn, maybe you can send Catalin an example mbox?
Attaching the one I used above.
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From: "=?UTF-8?q?Christian=20K=C3=B6nig?=" <ckoenig.leichtzumerken@xxxxxxxxx>
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To: helgaas@xxxxxxxxxx,
bhelgaas@xxxxxxxxxx,
linux-kernel@xxxxxxxxxxxxxxx,
linux-pci@xxxxxxxxxxxxxxx
Subject: [PATCH] x86/PCI: apply the AMD window fixup on resume as well
Date: Tue, 16 Jan 2018 10:43:17 +0100
Message-Id: <20180116094317.1603-1-christian.koenig@xxxxxxx>
X-Mailer: git-send-email 2.11.0
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We need to reprogram the register content during resume.
Signed-off-by: Christian König <christian.koenig@xxxxxxx>
Reported-by: Tom St Denis <tom.stdenis@xxxxxxx>
---
arch/x86/pci/fixup.c | 32 ++++++++++++++++++++------------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index f6a26e3cb476..8f3b1a6278e6 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -662,11 +662,11 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);
*/
static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
{
+ static const char *name = "PCI Bus 0000:00";
+ struct resource *res, *conflict;
u32 base, limit, high;
struct pci_dev *other;
- struct resource *res;
unsigned i;
- int r;
if (!(pci_probe & PCI_BIG_ROOT_WINDOW))
return;
@@ -707,21 +707,26 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
* Allocate a 256GB window directly below the 0xfd00000000 hardware
* limit (see AMD Family 15h Models 30h-3Fh BKDG, sec 2.4.6).
*/
- res->name = "PCI Bus 0000:00";
+ res->name = name;
res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM |
IORESOURCE_MEM_64 | IORESOURCE_WINDOW;
res->start = 0xbd00000000ull;
res->end = 0xfd00000000ull - 1;
- r = request_resource(&iomem_resource, res);
- if (r) {
+ conflict = request_resource_conflict(&iomem_resource, res);
+ if (conflict) {
kfree(res);
- return;
- }
+ if (conflict->name != name)
+ return;
- dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n",
- res);
- add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
+ /* We are resuming from suspend, just reprogram the regs. */
+ res = conflict;
+ } else {
+ dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n",
+ res);
+ add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
+ pci_bus_add_resource(dev->bus, res, 0);
+ }
base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) |
AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK;
@@ -733,13 +738,16 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high);
pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit);
pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base);
-
- pci_bus_add_resource(dev->bus, res, 0);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
#endif
--
2.11.0
