On Wed, Aug 23, 2017 at 02:08:54PM +0800, Zhiqiang Hou wrote: > From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx> > > Use the accessors instead accessing the DBI read-only write enable > register directly. This patch and the previous one (that added dw_pcie_dbi_ro_wr_en()) should be squashed together. That way it's obvious that the new code here is equivalent to the old code > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx> > Acked-By: Joao Pinto <jpinto@xxxxxxxxxxxx> > --- > V4: > - no change > > drivers/pci/dwc/pci-layerscape.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c > index 44a603db217a..0c1330fce01d 100644 > --- a/drivers/pci/dwc/pci-layerscape.c > +++ b/drivers/pci/dwc/pci-layerscape.c > @@ -33,7 +33,6 @@ > > /* PEX Internal Configuration Registers */ > #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ > -#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */ > > #define PCIE_IATU_NUM 6 > > @@ -145,10 +144,10 @@ static int ls_pcie_host_init(struct pcie_port *pp) > */ > ls_pcie_disable_outbound_atus(pcie); > > - iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN); > + dw_pcie_dbi_ro_wr_en(pci); > ls_pcie_fix_class(pcie); > ls_pcie_clear_multifunction(pcie); > - iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN); > + dw_pcie_dbi_ro_wr_dis(pci); > > ls_pcie_drop_msg_tlp(pcie); > > -- > 2.14.1 >
