Hi Stanimir, Thanks for your feedback! > -----Original Message----- > From: Stanimir Varbanov [mailto:svarbanov@xxxxxxxxxx] > Sent: 2017年8月16日 19:34 > To: Z.q. Hou <zhiqiang.hou@xxxxxxx>; linux-pci@xxxxxxxxxxxxxxx; > bhelgaas@xxxxxxxxxx; jingoohan1@xxxxxxxxx; Joao.Pinto@xxxxxxxxxxxx > Cc: M.h. Lian <minghuan.lian@xxxxxxx>; Mingkai Hu <mingkai.hu@xxxxxxx>; > Roy Zang <roy.zang@xxxxxxx>; niklas.cassel@xxxxxxxx; > jesper.nilsson@xxxxxxxx > Subject: Re: [PATCHv3 6/9] PCI: designware: add accessors for write > permission of DBI read-only registers > > Hi, > > On 08/16/2017 07:56 AM, Zhiqiang Hou wrote: > > From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx> > > > > The read-only DBI registers can be written over the DBI when set the > > "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the > > MISC_CONTROL_1_OFF register. > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx> > > --- > > V3: > > - No change > > > > drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++ > > 1 file changed, 25 insertions(+) > > > > diff --git a/drivers/pci/dwc/pcie-designware.h > > b/drivers/pci/dwc/pcie-designware.h > > index 7366c81..0c5f874 100644 > > --- a/drivers/pci/dwc/pcie-designware.h > > +++ b/drivers/pci/dwc/pcie-designware.h > > @@ -76,6 +76,9 @@ > > #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) > > #define PCIE_ATU_UPPER_TARGET 0x91C > > > > +#define PCIE_MISC_CONTROL_1_OFF 0x8BC > > +#define PCIE_DBI_RO_WR_EN (0x1 << 0) > > Does those registers exist for dwc version 4.01a? Joao, can you help to check this? I referred to DesignWare cores PCI Express controller databook version 4.21a. The Freescale Layerscape implement does not export the version of designware PCIe controller, I don't know which versions have those registers, if it does not work on qcom platform, I will remove the qcom related changes. > > I managed to test 6/9, 8/9 and 9/9 on qcom platform (apq8064) which has > 4.01a version and it doesn't work, i.e. the PCI_CLASS_BRIDGE_PCI is not > returned when read PCI_CLASS_DEVICE offset. > > > + > > /* > > * iATU Unroll-specific register definitions > > * From 4.80 core version the address translation will be made by > > unroll @@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct > dw_pcie *pci, u32 reg) > > return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4); } > > > > +static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) { > > + u32 reg; > > + u32 val; > > + > > + reg = PCIE_MISC_CONTROL_1_OFF; > > + val = dw_pcie_readl_dbi(pci, reg); > > + val |= PCIE_DBI_RO_WR_EN; > > + dw_pcie_writel_dbi(pci, reg, val); > > +} > > + > > +static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) { > > + u32 reg; > > + u32 val; > > + > > + reg = PCIE_MISC_CONTROL_1_OFF; > > + val = dw_pcie_readl_dbi(pci, reg); > > + val &= ~PCIE_DBI_RO_WR_EN; > > + dw_pcie_writel_dbi(pci, reg, val); > > +} > > + > > #ifdef CONFIG_PCIE_DW_HOST > > irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); void > > dw_pcie_msi_init(struct pcie_port *pp); > > Thanks, Zhiqiang
