On Mon, Jun 19, 2017 at 03:20:29PM +0530, Kishon Vijay Abraham I wrote: > > for writes to BARs - is this and intentional omission? It seems > > like the only current option is to poll for changes. > > You mean write to the address that's mapped to BAR in the EP side? > > PCI doesn't allow hosts to interrupt the EP (AFAIK), so we have to poll for any > writes by the host to EP memory. At least out on the bus each MMIO access translates to PCIe Memory Read/Write TLPs, so the EP itself for sure gets a notification. I don't really know enough about existing programmable endpoint IP to know how that could be forwarded to software, though.
