From: Robin Murphy
> Sent: 10 March 2017 15:23
...
> >> So you have 128MB (max) of system memory that has cpu physical
> >> addresses 0x80000000 upwards.
> >> I'd expect it all to be accessible from any PCIe card at some PCIe
> >> address, it might be at address 0, 0x80000000 or any other offset.
> >>
> >> I don't know which DT entry controls that offset.
> >
> > This is a crucial point, I think.
>
> The appropriate DT property would be "dma-ranges", i.e.
>
> pci@... {
> ...
> dma-ranges = <(PCI bus address) (CPU phys address) (size)>;
> }
Isn't that just saying which physical addresses the cpu can assign
for buffers for those devices?
There is also an offset between the 'cpu physical address' and the
'dma address'.
This might be implicit in the 'BAR0' base address register.
> The fun part is that that will only actually match the hardware once the
> magic BAR has actually been programmed with (bus address), so you end up
> with this part of your DT being more of a prophecy than a property :)
The BAR0 values could easily be programmed into the cpld/fpga - so
not need writing by the cpu at all.
David
