On 10/03/2017 16:14, David Laight wrote: > Mason wrote: > >> My RC drops packets not targeting its BAR0. > > I suspect the fpga/cpld logic supports RC and endpoint modes > and is using much the same names for the registers (and logic > implementation). Your guess is spot on. In the controller's MMIO registers, the so-called core_conf_0 register has the following field: chip_is_root: 1 means tango is root port, 0 means tango is endpoint. > If your cpu support more than 1GB of memory but only part is > PCIe accessible you'll have to ensure that all the memory > definitions are set correctly and 'bounce buffers' used for > some operations. Do you mean I would have to "fix" something in the XHCI driver? Hopefully, no customer plans to give Linux more than 1 GB. (Although the latest systems do support 4 GB... A lot of it is used for video buffers, handled outside Linux.) Regards.
