Hi Keith One thing that I do not understand > -----Original Message----- > From: linux-pci-owner@xxxxxxxxxxxxxxx [mailto:linux-pci- > owner@xxxxxxxxxxxxxxx] On Behalf Of Gabriele Paoloni > Sent: 30 January 2017 11:56 > To: keith.busch@xxxxxxxxx > Cc: linux-pci@xxxxxxxxxxxxxxx; Linuxarm; liudongdong (C); zhangjukuo; > Wangzhou (B) > Subject: Question: PCIe DPC not allowing for link retraining and bus > re-scan > > Hi Keith > > I am looking at the current DPC implementation in: > http://lxr.free-electrons.com/source/drivers/pci/pcie/pcie-dpc.c > > > If my understanding is correct upon an incoming DPC event > the DPC IRQ handler will: > 1) stop and remove all the devices in the hierarchy under the > downstream port that raised the event > 2) wait for the data link to be inactive > 3) keep the downstream port status in DPC (in fact we set the DPC > trigger status again here: > http://lxr.free-electrons.com/source/drivers/pci/pcie/pcie- > dpc.c#L55) As you can see above, after waiting for the link to be inactive we raise again a DPC event (according to PCIe3.0 6.2.10.1 we have DPC Interrupt Enable bit set to 1b and we set DPC Interrupt Status bit to 1b), also we keep the port in DPC status as we set also "DPC Trigger Status" to 1b. However this seems wrong to me as I would expect SW to clear "DPC Trigger Status" to allow the link to retrain and then to raise the Hot-plug event... What do you think? Thanks Gab [...]
