Hi Keith I am looking at the current DPC implementation in: http://lxr.free-electrons.com/source/drivers/pci/pcie/pcie-dpc.c If my understanding is correct upon an incoming DPC event the DPC IRQ handler will: 1) stop and remove all the devices in the hierarchy under the downstream port that raised the event 2) wait for the data link to be inactive 3) keep the downstream port status in DPC (in fact we set the DPC trigger status again here: http://lxr.free-electrons.com/source/drivers/pci/pcie/pcie-dpc.c#L55) Now looking at the specs we have (section 6.2.10): "After software releases the Downstream Port from DPC, the associated Link will normally attempt to retrain. Software can use Data Link Layer State Changed interrupts, DL_Active ERR_COR signaling, or both, to signal when the Link reaches the DL_Active state again" So if my understanding is correct in the current Linux implementation It is not possible to recover a PCIe hierarchy from a DPC event, is it correct? If this is correct, shouldn't we change the current implementation to release the port from DPC and re-scan the secondary bus after the conditions described in "PCIe 3.1 section 6.2.10" are met (I.e. <<Data Link Layer Link Active bit in the 15 Link Status register reads 0b>> and if it is a root port also <<until the DPC RP Busy bit reads 0b>>) ? Many Thanks Gab -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
