On Mon, Oct 31, 2016 at 04:39:02PM -0500, Bjorn Helgaas wrote: > Hardware that supports only 32-bit config writes is not spec-compliant. > For example, if software performs a 16-bit write, we must do a 32-bit read, > merge in the 16 bits we intend to write, followed by a 32-bit write. If > the 16 bits we *don't* intend to write happen to have any RW1C (write-one- > to-clear) bits set, we just inadvertently cleared something we shouldn't > have. > > Add a rate-limited warning when we do sub-32 bit config writes. Remove > similar probe-time warnings from some of the affected host bridge drivers. > > Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> > --- > drivers/pci/access.c | 17 +++++++++++++++-- > drivers/pci/host/pcie-hisi.c | 2 -- > drivers/pci/host/pcie-rockchip.c | 3 --- > 3 files changed, 15 insertions(+), 7 deletions(-) Yeah, this is a good idea: Acked-by: Thierry Reding <treding@xxxxxxxxxx> ----------------------------------------------------------------------------------- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. -----------------------------------------------------------------------------------
Attachment:
signature.asc
Description: PGP signature
