On Fri, 2016-06-10 at 15:28 +1000, Alexey Kardashevskiy wrote: > > Actually, it's likely caused by hardware defect > > - we can't set 2GB (0x80000000 - 0xffffffff) to RC's memory window. > > Otherwise, it *seems* the window is disabled. I tried updating the > > window with (0x80000000 - 0xffefffff) or (0x80000000 - 0xffdffff), no > > EEH error was seen. I already got 0x00001000 on read despite whatever > > I wrote to 0x20 reg. > > > > The hardware is broken. In order to fix this, I intend to include a > > bitmap for every PHB device node in skiboot. Kernel uses this to apply > > fixup accordingly. One bit is reserved on Garrison platform to avoid > > this issue. The fix can be a patch inserted before this patch in next > > revision > > This sounds better as preserves bisectability. Thanks. Ah yes they made those registers read-only. Look at my PHB4 code, I implement a cache for them in SW. Cheers, Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
