Tim Harvey <tharvey <at> gateworks.com> writes: > >> > >> Is there some sort of DT or OF spec that lists "max-link-speed" as a > >> generic property? I see Lucas' desire to have this be common across > >> DesignWare PCIe cores. Should it be moved up a level even from there, > >> i.e., to bindings/pci/pci.txt? > > > > Bjorn, > > > > I don't know what the general consensus is here. As your the PCI > > maintainer I would leave that up to you. Are there other platforms > > that need to link at a lesser capability than the host controller is > > capable of? I am only aware of the IMX6 and SPEAr13XX [1] > > > > I can make that change and re-submit if you feel that is necessary. > > > > Bjorn, > > Any thoughts here? I would really like to see this get picked up > sooner rather than later. > > Regards, > > Tim > Bjorn, It looks like there was no further follow-up on this patch. Could you kindly provide feedback to Tim's question? We have multiple i.MX boards that could use this patch to resolve PCIe issues. Thanks, Akshay -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
