On 2015/8/29 0:54, Thomas Gleixner wrote: > On Thu, 27 Aug 2015, Keith Busch wrote: > >> This patch adds struct x86_msi_ops to x86's PCI sysdata. This gives a >> host bridge driver the option to provide alternate MSI Data Register >> and MSI-X Table Entry programming for devices in PCI domains that do >> not subscribe to usual "IOAPIC" format. > > I'm not too fond about more ad hoc indirection and special casing. We > should be able to handle this with hierarchical irq domains. Jiang > might have an idea how to do that for your case. Hi Thomas and Keith, I have noticed this patch set yesterday, but still investigating the better way to handle this. Basically I think we should build per-domain/per-bus/per-device PCI MSI irqdomain, just like what ARM have done. That will give us a clear picture. But I need more information about the hardware topology to correctly build up the hierarchical irqdomain, especially the relationship between the embedded host bridge and IOMMU units. Keith, could you please help to provide some doc with hardware details? Thanks! Gerry -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
