> -----Original Message----- > From: Rajat Jain [mailto:rajatjain@xxxxxxxxxxx] > Sent: Tuesday, February 10, 2015 1:52 PM > To: Jake Oshins; linux-pci@xxxxxxxxxxxxxxx > Cc: Stu Grossman; Guenter Roeck > Subject: RE: 64bit BARs: prefetchable only? > > > , and the concept of prefetchable > > doesn't apply to Express. Bridges aren't allowed to buffer reads with > > Express, and so nothing is actually prefetched. > > Can you please point me to the section in the PCI Express spec that mandates > this? The only reference I could find in the spec to this was in an > "implementation note" below: > > ================================================================ > ======== > "Implementation Note: Additional Guidance on the Prefetchable Bit in Memory > Space BARs" > ================================================================ > ======= > ... > <snip> > ... > On PCI Express systems that meet the criteria enumerated below, setting the > Prefetchable bit in a > candidate BAR will still permit correct operation even if the BAR's range > includes some locations > that have read side-effects or cannot tolerate write merging. This is primarily > due to the fact that > PCI Express Memory Reads always contain an explicit length, and PCI Express > Switches never > prefetch or do byte merging. Generally only 64-bit BARs are good candidates, > since only Legacy > Endpoints are permitted to set the Prefetchable bit in 32-bit BARs, and most > scalable platforms map > all 32-bit Memory BARs into non-prefetchable Memory Space regardless of the > Prefetchable bit > value. > ... > <snip> > ... > ================================================================ > ======== This is exactly the section that I would have pointed you to. PCI Express switches are called switches rather than bridges because they do no buffering. When your endpoint has credits to put TLPs on the fabric, that means that those TLPs are going to pass all the way across the fabric. Your endpoint will never have credits when this can't happen. Thus there's no notion of prefetching. If you want a more detailed discussion than the implementation note above, read the sections on how an endpoint is granted the right to send TLPs. > I did not get this. How does it work if I map a 64 bit BAR using non-prefetchable > region, if there is no way for the bridges to forward the traffic to it (The > memory base and limit registers are only 32 bit)? > If you map a 64-bit BAR into a non-prefetchable region, that will involve writing zeros to all the bits in the upper part of the 64-bit BAR, so that it falls within the bridge windows. (This is strictly true only for endpoints which are not embedded in the root complex. These can appear on the root bus, and thus they might have addresses above 4GB in their BARs.) And yes, in my opinion, this makes the requirement that all BARs be 64-bit capable (on Express) a little silly. -- Jake Oshins -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
