> Hello, > > I'm working on a system that can potentially have a large amount of PCI > memory requirements (say 8GB or more) for the memory mapped PCI device > registers. Since these are registers, I want non-prefetchable memory windows > and not prefetchable ones. > > Now, I'm taking a look at the PCI-to-PCI bridge architecture specifications, and I > see that for bridges (downstream ports / root oorts etc), while there are 64 bits > available to specify the Prefetchable memory base and limit, the (non- > prefetchable) memory base and limit register are only 32 bit. I looked at > various different specs related to PCI, but I could not find anything that could > help me understand how to program a bridge so that it forwards a transaction > to a 64bit BAR, using the Non-prefetchable windows. > > My questions: > > 1) Is there any way possible to have a non-prefetchable memory, greater than > 4GB, programmed on a PCI bridge? > No, there isn't, but it probably doesn't matter in practice. You're almost certainly dealing with PCI Express here, and the concept of prefetchable doesn't apply to Express. Bridges aren't allowed to buffer reads with Express, and so nothing is actually prefetched. The prefetchable bit in the BAR is legacy from PCI, which did involve buffering in bridges. > 2) Is it possible to have to program a non-prefetchable window, may be small > size (say 1MB), but starts at a PCI address ABOVE 4GB? > No, but see the answer above. > 3) How do the 64 bit BARs behave. Does the PCI standard requires all 64 bit > BARs to be only mapped using prefetchable regions? > No, it doesn't. Cheers, Jake Oshins -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
