Am Montag, den 20.10.2014, 13:25 +0800 schrieb Richard Zhu:
> From: Richard Zhu <r65037@xxxxxxxxxxxxx>
>
> if va_cfg0_base/va_cfg1_base are initialized by
> designware core, the pp->cfg.start is not initialized
> properly, when IORESOURCE_MEM "config" is represented
> as cfg space resource.
> solution: assign cfg_res->start to pp->cfg.start.
>
> Signed-off-by: Richard Zhu <richard.zhu@xxxxxxxxxxxxx>
> ---
> drivers/pci/host/pcie-designware.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 8d1c809..e3cd54a 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -472,6 +472,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> if (cfg_res) {
> pp->config.cfg0_size = resource_size(cfg_res)/2;
> pp->config.cfg1_size = resource_size(cfg_res)/2;
> + pp->cfg.start = cfg_res->start;
> pp->cfg0_base = cfg_res->start;
> pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
>
I think this patch should not be needed anymore. Please look at commit
ec98e9ab6f24 (PCI: designware: Fix configuration base address when using
'reg') in 3.18-rc1. I think it fixes the same bug, but in a different
way. Can you confirm that this works for you?
Regards,
Lucas
--
Pengutronix e.K. | Lucas Stach |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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