RE: [PATCH v5 8/9] ARM: imx6sx: add imx6sx pcie related gpr bits definitions

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> -----Original Message-----
> From: linux-pci-owner@xxxxxxxxxxxxxxx [mailto:linux-pci-owner@xxxxxxxxxxxxxxx]
> On Behalf Of Lucas Stach
> Sent: Sunday, October 12, 2014 10:38 PM
> To: Richard Zhu
> Cc: linux-pci@xxxxxxxxxxxxxxx; Guo Shawn-R65073; festevam@xxxxxxxxx;
> tharvey@xxxxxxxxxxxxx; Zhu Richard-R65037
> Subject: Re: [PATCH v5 8/9] ARM: imx6sx: add imx6sx pcie related gpr bits
> definitions
> 
> Am Freitag, den 10.10.2014, 13:41 +0800 schrieb Richard Zhu:
> > From: Richard Zhu <r65037@xxxxxxxxxxxxx>
> >
> > Signed-off-by: Richard Zhu <richard.zhu@xxxxxxxxxxxxx>
> 
> You are using those defines in the PCIe driver changes, so the need to be
> sorted before them in the series as they need to be picked up by Bjorn to make
> sure we don't introduce build regressions.
> 
[Richard] Thanks for your kindly review.
Ok, would be placed just behind the modifications of the design-ware codes.

> > ---
> >  include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
> > b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
> > index ff44374..3273b87 100644
> > --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
> > +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
> > @@ -301,6 +301,7 @@
> >  #define IMX6Q_GPR12_DEVICE_TYPE			(0xf << 12)
> >  #define IMX6Q_GPR12_PCIE_CTL_2			BIT(10)
> >  #define IMX6Q_GPR12_LOS_LEVEL			(0x1f << 4)
> > +#define IMX6Q_GPR12_LOS_LEVEL_9			(0x9 << 4)
> >
> >  #define IMX6Q_GPR13_SDMA_STOP_REQ		BIT(30)
> >  #define IMX6Q_GPR13_CAN2_STOP_REQ		BIT(29)
> > @@ -395,4 +396,12 @@
> >  #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK    (0x3 << 17)
> >  #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK    (0x1 << 14)
> >
> > +/* For imx6sx iomux gpr register field define */
> > +#define IMX6SX_GPR5_PCIE_BTNRST			BIT(19)
> > +#define IMX6SX_GPR5_PCIE_PERST			BIT(18)
> > +
> > +#define IMX6SX_GPR12_PCIE_PM_TURN_OFF		BIT(16)
> > +#define IMX6SX_GPR12_PCIE_TEST_PD		BIT(30)
> > +#define IMX6SX_GPR12_RX_EQ_MASK			(0x7 << 0)
> > +#define IMX6SX_GPR12_RX_EQ_2			(0x2 << 0)
> >  #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
> 
> 
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Best Regards
Richard Zhu
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