On Fri, Oct 10, 2014 at 2:41 AM, Richard Zhu <richard.zhu@xxxxxxxxxxxxx> wrote:
> + pinctrl_pcie: pciegrp {
> + fsl,pins = <
> + MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x17059
Why 0x17059 instead of the default 0x10b0?
> + >;
> + };
> +
> + pinctrl_pcie_reg: pciereggrp {
> + fsl,pins = <
> + MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x17059
Same here.
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