On Thu, Mar 27, 2014 at 12:49 PM, shiv prakash Agarwal <chhotu.shiv@xxxxxxxxx> wrote: > Thanks Bjorn, > >>>A host bridge, e.g., a PCIe root complex, claims the transaction and issues a corresponding PCI or PCIe transaction. This is where the host bridge may optionally convert the CPU physical address to a different PCI bus address. > > So it means this read(i.e readl(ioremap(pci_resource_start()))) > follows all PCIE layers and thus happening through PCIe interface? Yes. >>>The transaction generated by the host bridge travels downstream, i.e., away from the CPU. > So both read and write here are generated by CPU(or host bridge) and > both these transaction travels downstream? Yes. > On Thu, Mar 27, 2014 at 9:09 PM, Bjorn Helgaas <bhelgaas@xxxxxxxxxx> wrote: >> On Thu, Mar 27, 2014 at 5:02 AM, shiv prakash Agarwal >> <chhotu.shiv@xxxxxxxxx> wrote: >>> I have a kernel space testcode which does below after all enumeration >>> and driver loading is done: >>> >>> 1. read BARx address of endpoint from its config space >> >> The BAR contains a PCI bus address. This is often, but not always, >> identical to the CPU physical address. To ioremap it, you must supply >> the CPU physical address, which you get from pci_resource_start(). >> >>> 2. ioremap this physical address to get virtual address >>> 3. read this virtual address using readl/readw api >> >> The CPU internally converts the virtual address to a physical address >> and issues a read transaction to the physical address. A host bridge, >> e.g., a PCIe root complex, claims the transaction and issues a >> corresponding PCI or PCIe transaction. This is where the host bridge >> may optionally convert the CPU physical address to a different PCI bus >> address. >> >> I'm not quite sure what you mean by "upstream or downstream traffic." >> The transaction generated by the host bridge travels downstream, i.e., >> away from the CPU. The response from the device then travels >> upstream, back towards the CPU, of course. But maybe you had some >> hardware detail in mind, and I'm not a hardware expert. >> >> You can also do writes the same way. >> >>> Query is: >>> >>> 1. Does read in point 3 above happens through PCIE interface? >>> 2. Is it upstream or downstream traffic? >>> 3. Could we do corresponding write also? >> >> Does this answer your questions? >> >> Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
