On Wed, Mar 19, 2014 at 3:01 PM, Bjorn Helgaas <bhelgaas@xxxxxxxxxx> wrote:
> On Wed, Mar 19, 2014 at 12:18 PM, Yinghai Lu <yinghai@xxxxxxxxxx> wrote:
>
> I think the current pciehp design is a bit broken. Today we perform
> commands very synchronously:
>
> pcie_write_cmd() {
> write Slot Control
> if (Command Complete supported) {
> wait for Command Complete
> }
> }
>
> The typical driver pattern would be more asynchronous, like this:
>
> pcie_write_cmd() {
> read Slot Status
> if (!Command Completed) {
> wait for Command Complete
> }
> write Slot Control
> }
>
> With the asynchronous pattern, we would probably never wait at all
> unless we performed two commands in immediate succession. I wouldn't
> be surprised if doing this asynchronously would effectively cover up
> these hardware differences.
I like this idea. Will give it a try.
Thanks
Yinghai
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