subject line
PCI: designware: Fix comment for setting number of lanes
~Rajeev
On 2/20/2014 10:52 AM, Mohit KUMAR wrote:
Corrects comment for setting number of lanes.
Signed-off-by: Mohit Kumar<mohit.kumar@xxxxxx>
Cc: Jingoo Han<jg1.han@xxxxxxxxxxx>
Cc: Bjorn Helgaas<bhelgass@xxxxxxxxxx>
Cc: spear-devel@xxxxxxxxxxx
Cc: linux-pci@xxxxxxxxxxxxxxx
---
drivers/pci/host/pcie-designware.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 6d23d8c..391966f 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -766,7 +766,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
u32 membase;
u32 memlimit;
- /* set the number of lines as 4 */
+ /* set the number of lanes */
dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL,&val);
val&= ~PORT_LINK_MODE_MASK;
switch (pp->lanes) {
--
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