Hello Bjorn, > -----Original Message----- > From: Bjorn Helgaas [mailto:bhelgaas@xxxxxxxxxx] > Sent: Thursday, February 20, 2014 3:24 AM > To: Mohit KUMAR DCG > Cc: jg1.han@xxxxxxxxxxx; Pratyush ANAND; Arnd Bergmann; spear-devel; > linux-pci@xxxxxxxxxxxxxxx > Subject: Re: [PATCH 1/1] Designware:RC BARs setup related fix > > On Wed, Feb 19, 2014 at 05:34:35PM +0530, Mohit Kumar wrote: > > The Synopsys PCIe core provides one pair of 32-bit BARs (BAR 0 and BAR > 1). > > The BARs can be configured as follows: > > > > - One 64-bit BAR: BARs 0 and 1 are combined to form a single 64-bit BAR. > > - Two 32-bit BARs: BARs 0 and 1 are two independent 32-bit BARs > > > > This patch corrects 64-bit, non-prefetchable memory BAR configuration > > implemented in dw driver. > > > > Signed-off-by: Mohit Kumar <mohit.kumar@xxxxxx> > > Cc: Pratyush Anand <pratyush.anand@xxxxxx> > > Cc: Jingoo Han <jg1.han@xxxxxxxxxxx> > > Cc: Arnd Bergmann <arnd@xxxxxxxx> > > Cc: spear-devel@xxxxxxxxxxx > > Cc: linux-pci@xxxxxxxxxxxxxxx > > Applied to pci/host-designware for v3.15, thanks! - thanks > > I update the summary to the following; let me know if it's not accurate: > > PCI: designware: Fix RC BAR to be single 64-bit non-prefetchable memory > BAR - yes, it looks better Thanks, Mohit -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
