On Wed, Feb 19, 2014 at 05:34:35PM +0530, Mohit Kumar wrote: > The Synopsys PCIe core provides one pair of 32-bit BARs (BAR 0 and BAR 1). > The BARs can be configured as follows: > > - One 64-bit BAR: BARs 0 and 1 are combined to form a single 64-bit BAR. > - Two 32-bit BARs: BARs 0 and 1 are two independent 32-bit BARs > > This patch corrects 64-bit, non-prefetchable memory BAR configuration > implemented in dw driver. > > Signed-off-by: Mohit Kumar <mohit.kumar@xxxxxx> > Cc: Pratyush Anand <pratyush.anand@xxxxxx> > Cc: Jingoo Han <jg1.han@xxxxxxxxxxx> > Cc: Arnd Bergmann <arnd@xxxxxxxx> > Cc: spear-devel@xxxxxxxxxxx > Cc: linux-pci@xxxxxxxxxxxxxxx Applied to pci/host-designware for v3.15, thanks! I update the summary to the following; let me know if it's not accurate: PCI: designware: Fix RC BAR to be single 64-bit non-prefetchable memory BAR > --- > drivers/pci/host/pcie-designware.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c > index 17ce88f..6d23d8c 100644 > --- a/drivers/pci/host/pcie-designware.c > +++ b/drivers/pci/host/pcie-designware.c > @@ -800,7 +800,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > > /* setup RC BARs */ > dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); > - dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1); > + dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); > > /* setup interrupt pins */ > dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val); > -- > 1.7.0.1 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majordomo@xxxxxxxxxxxxxxx > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
