Hi Arnd / Jingoo, Sorry for not able to follow earlier discussion you had on this topic while initial reviews of patches from Jingoo. I have few doubts that how will it actually work. As per my understanding under current implementation: 1. Physical IO addresses are in the range of 0x1000 to 0xfffff. 2. They are mapped to fixed virtual address 0xFEE00000 using pci_ioremap_io. 3. IO resource addresses to any PCIe device will be allocated in above range. 4. Driver for that PCIe device will write in the above range only for IO transaction to the device. 5. As per current IO translation programming, its one to one translation. It means PCIe translation unit will have both input and output address in the range of 0x1000 to 0xfffff. Did I miss something, or if above statements are correct, then what I do not understand is how can designware PCIe translation unit accept input address in the range of 0x1000 to 0xfffff? For example in SPEAr1340, physically RAM is mapped on above addresses. PCIe address translation unit can accept address only in the range of core addresses which are assigned to PCIe RC ie 0x80000000-0x8FFFFFFF. Regards Pratyush -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
