If 32-bit prefetchable BARs detected, the prefetchable resource's IORESOURCE_MEM_64 flag of its upstream bridge will be reset. This in turn causes all upstream bridges up to the root bridge have their IORESOURCE_MEM_64 reset. If prefetchable windows in a system located above 4G, then they are never used for the sake of 32-bit prefetchable BAR. Desert 64-bit prefetchable windows for ROM BAR seems unreasonable. Just don't reset bridge's IORESOURCE_MEM_64 flag in case of ROM BARs. They will fail to get address from 4G-above prefetchable window and fall back to non-prefetchable window within 4G. Signed-off-by: Guo Chao <yan@xxxxxxxxxxxxxxxxxx> --- drivers/pci/setup-bus.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 4ce83b2..e9006b9 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -974,7 +974,8 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, aligns[order] += align; if (order > max_order) max_order = order; - mem64_mask &= r->flags & IORESOURCE_MEM_64; + if (i != PCI_ROM_RESOURCE) + mem64_mask &= r->flags & IORESOURCE_MEM_64; if (realloc_head) children_add_size += get_res_add_size(realloc_head, r); -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
