> > "Grumbach, Emmanuel" <emmanuel.grumbach@xxxxxxxxx> writes: > > > Ok - so I have now the complete picture. > > > This device was designed before PCI-SIG gave an ID to L1 PM Substates, > > so Intel had to use the L1 PM Substate as a Vendor Define whose ID is > > 0xCAFE. Layout is the same as defined now in PCI-SIG (page 21 in > > > http://www.pcisig.com/specifications/pciexpress/specifications/ECN_L1_PM > _Substates_with_CLKREQ_31_May_2013_Rev10a.pdf). > > > > So: > > 150: 03 10 03 10 0b 00 01 00 fe ca 41 01 1f 1e f0 00 > > 160: 0f 00 a0 40 f0 00 00 00 00 00 00 00 00 00 00 00 > > > > We can see that L1 PM Substate *is* enabled: > > 004h = 41 01 1f 1e > > 008h = 0f 00 f0 00 > > 00Ch = a0 40 f0 00 > > Wow! That's extremely useful. > > But I do have some problems placing the individiual bits right in these LE > registers. And so have you, I believe... You are 2 bytes off. > "41 01" is part of the vendor specific header (12 bits length == 0x014 and 4 > bits version == 0x1. > yeah - it seemed awkward to me that the header isn't 4-bytes aligned, but some bits seemed ... strange then. So I opted to the that (wrong) parsing. My poor brain has always issues parsing this kind of things and take in count the endianity etc.. :) > So I made a simple patch for lspci based on your info. Seems to work for me: > > > 03:00.0 Network controller [0280]: Intel Corporation Wireless 7260 > [8086:08b1] (rev 63) > Subsystem: Intel Corporation Dual Band Wireless-AC 7260 > [8086:4070] > Physical Slot: 1 > Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- > ParErr- Stepping- SERR+ FastB2B- DisINTx+ > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- > <TAbort- <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 64 bytes > Interrupt: pin A routed to IRQ 45 > Region 0: Memory at f0500000 (64-bit, non-prefetchable) [size=8K] > Capabilities: [c8] Power Management version 3 > Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1- > ,D2-,D3hot+,D3cold+) > Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit+ > Address: 00000000fee0100c Data: 4152 > Capabilities: [40] Express (v2) Endpoint, MSI 00 > DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency > L0s <512ns, L1 unlimited > ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ > DevCtl: Report errors: Correctable- Non-Fatal- Fatal- > Unsupported- > RlxdOrd+ ExtTag- PhantFunc- AuxPwr+ NoSnoop+ > FLReset- > MaxPayload 128 bytes, MaxReadReq 128 bytes > DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- > AuxPwr+ TransPend- > LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s > L1, Exit Latency L0s <4us, L1 <32us > ClockPM+ Surprise- LLActRep- BwNot- > LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+ > ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ > DLActive- BWMgmt- ABWMgmt- > DevCap2: Completion Timeout: Range B, TimeoutDis+, LTR+, > OBFF Via WAKE# > DevCtl2: Completion Timeout: 16ms to 55ms, TimeoutDis-, > LTR-, OBFF Disabled > LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- > SpeedDis- > Transmit Margin: Normal Operating Range, > EnterModifiedCompliance- ComplianceSOS- > Compliance De-emphasis: -6dB > LnkSta2: Current De-emphasis Level: -3.5dB, > EqualizationComplete-, EqualizationPhase1- > EqualizationPhase2-, EqualizationPhase3-, > LinkEqualizationRequest- > Capabilities: [100 v1] Advanced Error Reporting > UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- > UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- > UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- > UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- > UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- > UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- > CESta: RxErr- BadTLP+ BadDLLP- Rollover- Timeout- > NonFatalErr+ > CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- > NonFatalErr+ > AERCap: First Error Pointer: 00, GenCap- CGenEn- > ChkCap- ChkEn- > Capabilities: [140 v1] Device Serial Number 0c-8b-fd-ff-ff-08-09-71 > Capabilities: [14c v1] Latency Tolerance Reporting > Max snoop latency: 0ns > Max no snoop latency: 0ns > Capabilities: [154 v1] Vendor Specific Information: ID=cafe Rev=1 > Len=014 L1 PM Substates > L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ > ASPM_L1.1+ L1_PM_Substates+ > PortCommonModeRestoreTime=30us > PortTPowerOnTime=60us > Kernel driver in use: iwlwifi > 00: 86 80 b1 08 06 05 10 00 63 00 80 02 10 00 00 00 > 10: 04 00 50 f0 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 70 40 > 30: 00 00 00 00 c8 00 00 00 00 00 00 00 0b 01 00 00 > 40: 10 00 02 00 c0 8e 00 10 10 0c 11 00 11 ec 06 00 > 50: 42 01 11 10 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 12 08 08 00 05 00 00 00 00 00 00 00 > 70: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 01 d0 23 c8 00 00 00 0d > d0: 05 40 81 00 0c 10 e0 fe 00 00 00 00 52 41 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 100: 01 00 01 14 00 00 00 00 00 00 00 00 31 20 46 00 > 110: 40 20 00 00 00 20 00 00 00 00 00 00 00 00 00 00 > 120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 140: 03 00 c1 14 71 09 08 ff ff fd 8b 0c 18 00 41 15 > 150: 00 00 00 00 0b 00 01 00 fe ca 41 01 1f 1e f0 00 > 160: 00 00 00 00 28 00 00 00 00 00 00 00 00 00 00 00 > 170: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 1a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 1b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 1c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 1e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 1f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 210: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [snipped the remaing 00 > bytes] > > > > I may have messed up things here... > > > > According to System / HW, it is unsafe to disable L1 PM Substate using > setpci, even if we disable it from both sides (device and bridge). This kind of > settings should be done by BIOS only. > > So we have 2 options here (assuming that we can't disable that in BIOS): > > * either we try to disable L1 PM Substate even my colleagues think it > > is not safe > > * either we just disable L1 altogether > > How about forcing ASPM even if the BIOS says it's unsupported? Has that > been tested? > Well... No... At least not by me. People usually care more about connectivity than saving power :) ��.n��������+%������w��{.n�����{���"�)�� jg��� �����ݢj����G���� ���j:+v���w�m������w�������h�����٥
